Whitepaper: A Brief Introduction to High Voltage Ceramic Capacitors

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High voltage multilayer ceramic capacitors (HVMLCC) are discussed from the standpoints of how they function, their internal and external design, the materials used, and important factors to consider for your applications and your respective high voltage circuit designs.

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Contents

 Chapter 1: High Voltage Ceramic Capacitors

High voltage multilayer ceramic capacitors (HVMLCC) are discussed from the standpoints of how they function, their internal and external design, the materials used, and important factors to consider for your applications and your respective high voltage circuit designs.

Surface mount high voltage multilayer ceramic capacitors (MLCCs) appear to be pretty much identical to standard configuration MLCCs. They have the same basic form, fit and function, but there are several key differences. For the purposes of this paper, as a matter of definition, high voltage MLCCs have rated voltages that are greater than or equal to 200VDC.

High voltage MLCCs (HVMLCCs) are typically available in EIA size from 0603 to 2225 or larger (metric 1608 to 5664) with voltage ratings from 200V to 5,000V or more. Smaller case high voltage MLCCs typically have lower maximum rated voltages (VRated) as the external terminals tend to be closer to each other in comparison to larger case high voltage MLCCs. High voltage MLCCs are generally available with Class 1 (C0G) or Class 2 (e.g., Ferroelectric X7R) ceramic dielectrics with tolerances that are as good as +/-5% or better, to as wide as +/-20% or higher. Because of the generally thicker dielectric thicknesses used in the design and potentially the “cascade” or “floating electrode” type designs used, the maximum capacitance values available are significantly lower than standard MLCCs. HVMLCCs are generally available in nominal capacitance values ranging from ~1 pF to 2.2 µF or higher. Equivalent series resistance (ESR) is also typically quite low (e.g., ≤10 mΩ). HVMLCCs appear similar to standard configuration MLCCs.

It seems that it should be straight forward to design an HVMLCC of a given voltage rating; just keep increasing the dielectric thickness (DT) to enable the voltage rating desired as you would with a standard configuration MLCC. The rate of increase in DT used is typically about 200 to 250 Volts per thousandth of an inch (V/mil, or ~7.8 to 10 V/µm). There is a penalty in capacitance per unit volume (C/V) using this approach to increasing rated voltage, as it requires increasing DT. The penalty in C/V is proportional to DT-2 following the relationship:

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  • C is capacitance (F)
  • V is volume (m3) ~
  • ε0 is the dielectric permittivity of free space (8.854×10-12 F/m)
  • ε’ is the real portion of the dielectric permittivity of the dielectric used between each electrode set (unitless)
  • n is the number of active layers in the MLCC configuration
  • An is the electrode overlap area per each active layer

However, above ~1,500V, it gets more complicated than that. An example of the resulting penalty to C/V is illustrated in Figure 1 below. As voltage rating is increased, DT must increase to the expense of C/V in a manner that is linear for the log-log relationship demonstrated on the right, where C/V is reduced 2 decade values for every one decade value increase in DT. Thus, as rated voltage is increased, capacitance per unit volume is reduced at a fairly dramatic rate.

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Figure 1. Approximate normalized capacitance vs. DT (linear (left) and log-log (right))

The above penalty in C/V as voltage rating is increased is not the only factor to consider however as the above as- sumes that a constant rate of increase in DT is appropriate to achieve increased voltage rating. While this is true, typically to ~1,000 to ~1,500VRated ceramic dielectrics tend deviate from that rate as VRated is increased above

~1,000 to ~1,500V, resulting in a different VRated vs. dielectric thickness relationship that is of lower slope. A hypo- thetical example of this is given in Figure 2 below.

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For the example, in Figure 2, if one desires to design an HVMLCC having rated voltage of 1,500 V, one must use the red line in Figure 2, which requires that a DT of ~10 mil (~250 µm) be used instead of the DT of 6 mil (~150 µm) that could be used if the blue linear model could be followed above ~1,250V. This results in a reduction of C/V by a factor of ~100 in comparison to a 250VRated, 1 mil DT MLCC instead of a reduction in C/V of ~36 fold if we could have, in some way, maintained the initial linear relationship (~200 to 250 V/mil) indicated by the blue line in Figure 2, which would have allowed use of a DT of ~6 mil. The resulting furthered penalty in C/V is and additional ~3 fold reduction in this case (i.e., the resulting maximum C/V would be almost 3 times as high for the blue line as com- pared to the red line in the case of 1,500VRated).

Thus, there is need for a better design for HVMLCCs. Capacitance values of capacitors placed in parallel in a circuit are additive, while in series they behave in a manner defined by the relation:

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Cn = Capacitance of capacitor n

If all of the capacitors in series have the same capacitance value, the above simplifies to:

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n is the number of capacitors in series, each having capacitance value Cn

Also, voltage ratings of capacitors in series increase linearly following the relation:

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n is the number of capacitors in series, each having voltage rating Vn

Using the above relationships, we can increase VRated linearly with a relatively small decrease in capacitance (~Cn/n). Thus, there is a need to be able to fit multiple capacitors in series within a single MLCC for HVMLCC applications. Floating electrode (FE) or cascade electrode design MLCCs were devised for this need in order to have more than one internal capacitor in series within the MLCC.

Floating electrode (FE) or cascade electrode designs are illustrated in comparison to a standard electrode configura- tion MLCC in Figure 3 below. From the illustration, it is evident that floating electrodes placed between externally connected electrodes result in 2 cascades (or capacitors in series) per each floating electrode segment used in the design. One and two FE (or 2 and 4 cascade) designs are illustrated. From the figure, we can see that the electrode active area (A) is reduced with each cascade as well as the MLCC case size does not change. Ignoring the dimension reduction caused by the additional internal margins, the active area is approximately halved for each floating elec- trode, while the rated voltage increases linearly with each internal capacitor in series.

Because of the reduction in A and the series effect described above, the resulting C/V (ignoring the additional internal margin areas created with each FE) is proportional to 1/n2 (where n is the number of cascades or capaci- tors in series created). This means that VRated can increase linearly as the number of FEs is increased, with a C/V penalty that is fairly close to the C/V penalty experienced with a standard capacitor configuration MLCC that uti- lizes increased DT to achieve desired VRated in the linear region below ~1,500 V (i.e., according to the blue line in Figure 2 above). For relatively large case MLCCs (typically EIA 1206 and larger) this provides a relatively favorable C/V solution for HVMLCCs for voltage ratings above ~1,500V.

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We can use FE or cascade electrode MLCCs to increase VRated with relatively minimized impact on C/V as com- pared to standard configuration MLCCs at lower voltages (i.e., <~1,000V to ~1,500V). As each FE has an additional margin area associated with it, the impact of additional margins on C/V in small case MLCCs (typically EIA 0603 and 0805) may be prohibitive, but for larger MLCCs (e.g., EIA 1206 to 2225) the impact is acceptable to relatively small. As in Figure 4 below, C/V decreases commensurate with (1/2n2), where n is the number of FEs within the design.  

VRated also increases with 2n as does ESR. The effect on ESR is largely compensated for however, as the two or more internal capacitors typically have more electrodes in each internal capacitor stack (N), thereby reducing ESR within each capacitor in series, and since the aspect ratio of said electrodes within each of the internal capacitors in series has relatively wide and short electrodes, which results in further decreased ESR. These two factors work together to reduce ESR such that the projected ESR increase is typically negligible, and may even be reduced in comparison to standard configuration MLCCs of similar VRated.

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Additionally, since FE design results in MLCCs having at least two internal capacitors in series, each of the internal capacitors must fail short in order for the FE MLCC to have an internal short, which is highly unlikely, making FE MLCC highly desirable for applications that are sensitive to short-type failures. Thus, in comparison to standard configuration MLCCs; with careful design, it is possible to achieve high VRated with minimal increase in ESR and decrease in C/V. It is also important to remember that the energy stored in a capacitor is related to the square of the voltage through the relationship:

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E is energy in Joules

C is capacitance in Farads V is voltage in Volts

This means that, even though HVMLCCs typically have much lower C/V values than standard MLCCs, they can store about the same amount of energy as a standard configuration MLCC at each designs’ respective rated volt- age. FE designs largely reduce or eliminate the possibility of short-type failures. This is because all of the cascades or internal capacitors must fail in order to create a short-type failure. Thus, failure due to flexure cracking or the like is largely mitigated in most cases.

This makes FE type MLCCs quite valuable in performance critical applications such as across a battery line or the like. High voltage MLCCs can also fail from external arcing or similar external phe- nomena. External failure usually results from at least one external arcing event, for one or more of several potential reasons.

First, it is important to control the minimum separation of the terminations to prevent arcing between the exter- nal terminals or terminations. HVMLCCs are typically as small as 0603 (EIA) case size. In that case, termination separation may be as narrow as ~0.047” (~1.2 mm) and maximum voltage rating (~250 VDC) is limited compared to larger case MLCCs with larger termination separations.  For example 1206 EIA case size HVMLCCs are avail- able with maximum VRated of ~3 KV. These HVMLCCs have minimum termination separation of about 0.073” (~1.85 mm). Additionally, 1808 EIA case size HVMLCCs are available with maximum VRated of ~5 KV, and these HVMLCCs have a minimum termination separation of about 0.128” (~3.25 mm)).

Next, it is important to note that all surfaces (e.g., 4 sides) between the two external terminals must be clean in order to maximize surface resistance between the terminals, as contamination tends to be more conductive than ceramic dielectrics. Additionally, it is important that the external surfaces separating the two terminals are also dense and smooth, as porosity and surface roughness can trap contamination and have lower surface resistance as well.

Surface arcing also depends upon ionization of the air immediately covering the surface of the area of the region that arcs. The “quasi-plasma” that is formed in the air in that region that enables the arcing is affected by the electric field that is associated with the internal structure of the MLCC (i.e., electrode design). Said “quasi-plasma” and associated electric field is affected by the dielectric constant (K) of material from which the arcing surface is made (i.e., Class 2 ceramic dielectrics, such as Y5V, X5R or X7R or the like have a higher propensity toward surface arcing at a given voltage than do Class 1 ceramic dielectrics such as C0G).  

Any impurities within the “quasi-plasma” that are formed in the air or space near the surface of the component, or on the surface of the component, can be deposited on the surface during arcing and may be converted in a manner that results in a relatively low resistance path between the two external terminals, thus resulting in surface arcing. When a low resistance path is formed in this manner, mul- tiple arcing events may occur along the same path, resulting in failure of the HVMLCC due to reduction in insulation resistance (IR).

 Chapter 2: Design Considerations

In general, HVMLCCs are used in numerous applications where high voltage (either AC or DC or both) are encoun- tered. HVMLCCs are carefully designed to perform correctly via careful dielectric selection, as well as via proper internal and external design in order to prevent surface arcing through a “quasi-plasma” that may be established due to electric fields encountered in the related application. This corona discharge is to be avoided as it will degrade and possibly destroy the HVMLCC or the surrounding circuitry.

It is also important to carefully design your circuit board so that the termination lands have maximized separation distance, and one must take care to avoid the use of solder fluxes that contain ionic species that could facilitate arcing either beneath the MLCC chip or on one or more of the sides of the chip during operation. Any residues resulting from surface mount (SMT) activities should be fully removed via proper cleaning of the board after SMT as well. Use of fluxes containing any residue during SMT operations should also be avoided. It may also be beneficial to add a conformal coating over the surface of the mounted and cleaned HVMLCCs and other mounted HV components in order to prevent surface arcing. The coating should have a high breakdown strength, combined with a high resistivity (surface and bulk), as well as high breakdown strength. Silicones tend to be ideal for this application. If something more mechanically rugged is needed, then an epoxy (typically difficult to rework) or a urethane (typically easier to rework) should be good.

Since the impedance of HVMLCCs can be quite low at high frequencies, it is important to understand the frequen- cies and voltages associated with your application. If the impedance of the HVMLCC selected is low at a frequency utilized a great amount of current may be passed through the device at that frequency if the voltage associated with that frequency is high. In these situations, it is highly important to understand the current carrying capacity (typi- cally called ripple current capability) of the HVMLCC selected for said application, as use of a device with inadequate ripple current capability may result in overheating of the component, and damage to the component and the circuit. It is also important to understand the voltages that the HVMLCC will experience as HVMLCCs typically have rela- tively low ESR values at relatively high frequencies.  AC applications utilizing frequencies >10 KHz, or applications that may include voltage surges, are especially important to evaluate carefully, as most voltage ratings are based on DC voltages, which may not be relevant at all to these situations.

For most relatively low frequency AC applications (i.e., less than ~10 KHz), it’s typically all right to select an HVMLCC having a VRated value that is about 2.8X that of the VRMS of the application, based upon the logic that VRated should be about the same as VP-P. At higher frequencies, as impedance decreases, this multiplier should increase. It is highly important for the designer to test the circuit to insure proper device selection for his or her spe- cific application. Testing will also inform the designer of other issues that should be remedied, such as piezoelectric buzzing, overheating or the like.  In these cases, redesign of the circuit or selection of a more appropriate HVMLCC is in order prior to sending the design to production.

There are many applications for HVMLCCs. Many of these applications require specially rated or certified devices (e.g., applications requiring safety rated capacitors and the like). The designer should always be familiar with all ap- plicable specifications and requirements; and should carefully specify each HVMLCC device accordingly. HMLCCs are used in numerous switching power supply circuits for numerous applications, and power supplies are a major area of application for HVMLCCs. For example, Cuk (pronounced “chook”) convertors are DC-DC convertors that use a capacitor for energy storage during the voltage conversion process. An example of a Cuk converter circuit is illustrated in Figure 5 below.

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In this type of design, the voltage across the capacitor (C) is typically:

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Vis the voltage across the capacitor Vis the output voltage

D is the duty cycle

From the above, it is evident that, depending upon the output voltage and the duty cycle used, the voltage on the HVMLCC in the Cuk converter can be quite high. HVMLCCs are also used in cold cathode fluorescent lamp (CCFL) driver circuits or lighting ballast circuits which typically require one or more HVMLCCs. High intensity dis- charge (HID) lamps also require similar boost-type power supplies which require HVMLCCs. HVMLCCs are also used in certain high brightness light emitting diode (HBLED) driver circuits as well as in certain camera flash strobe circuits. Other examples include snubber circuits in switch mode power supplies (SMPS) that reduce or eliminate voltage transients from MOSFET (metal oxide field effect transistor) switching events or the like, as well as resonator circuits, high voltage blocking circuits, high voltage coupling circuits, and input and output filter capacitors in power supply circuitry. These are all common applications for HVMLCCs.

HVMLCCs are also used in general high voltage circuit applications, such as voltage multipliers, RF power circuits, and general applications requiring high voltage DC blocking or AC coupling. Additionally, HVMLCCs are used in general applications where voltage surge suppression is required such as LAN products, including but not limited to, LAN/WAN interfaces, Ethernet switches, and analog and digital modems.  They may also be used for DC blocking in modems for tip and ring applications. HVMLCCs are becoming more popular in automotive applications as well, and are used in numerous telecommunications, medical and military/aerospace/space applications. This is especially true for the latter with the increasing popularity of “fly by wire” technology. As HVMLCCs typically have very high insulation resistance (IR), they are also popular for use with high temperature semiconductors (e.g., silicon on insula- tor (SoI) or the like), and in elevated temperature applications, as well as in specialized test and diagnostic equipment. HVMLCCs with floating electrode (FE) designs are also an excellent choice when the device is to be used across a battery line or application that should never fail short.

For space and vacuum applications, it is very important that the HV circuit be properly designed in order to prevent surface arcing or corona discharge, as the “quasi-plasma” may become “real plasma” in the vacuum, and corona dis- charge is more likely at lower voltages at the relatively low gas pressures encountered in near space. There are numer- ous excellent HV design guides for HV circuit boards that cover HV design and component selection.

 Chapter 3: Summary

Floating electrode (FE) or cascade internal electrode designs may be used to increase VRated of MLCCs with minimal impact on ESR and capacitance per unit volume (C/V) in comparison to standard configuration MLCCs. Additionally, FE designs largely reduce or eliminate the possibility of short-type failures and thus are valuable in battery line and other critical applications. For these reasons, floating electrode or cascade electrode designs are typically superior to standard configuration designs for high voltage applications.

Use of wider terminal separations and lower K dielectrics typically result in a more robust HVMLCC with respect to rated voltage.  It may be prudent to use Class 1 dielectric (e.g., C0G, etc.) HVMLCCs whenever possible and if Class 2 dielectrics are necessary, to use X7R dielectrics in favor of X5R or Y5V dielectrics as they typically have higher K than X7R dielectrics and may result in external arcing at lower voltages. The surfaces of the HVMLCCs used should be dense, smooth and clean as well for HV applications.

The designer must always be sure to choose the right HVMLCC for his or her application, considering all of the voltages, transients, and frequencies as well as ripple voltages/currents involved.  It is important to comply with all applicable certification and specification requirements. The designer should always design and to test his or her circuit carefully to ensure proper function and reliability. The designer should also keep in mind that floating electrode (FE) HVMLCCs rarely fail short, and thus are good for battery line applications in addition to all of the HV applications noted above.

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