SMT Chips and Shelf Life
Have you ever wondered why that chip component sitting in your inventory has a shelf life? These capacitors, resistors and inductors are made mostly with ceramic materials that definitely don’t spoil! After all, reliability testing predicts that these products should last for years (sometimes hundreds, if not thousands) in service. So why does the manufacturer recommend that you use them within 6 to 18 months of the date of manufacture?
Well, it comes down to solderability. Manufacturers explain that the chip finish (e.g. tin) oxidizes over time and thus becomes less solderable. While that’s true, it’s a little more complicated than that. In addition to the oxidation of the tin, intermetallic (IMC) growth that can also hinder solderability.
Most SMT chip terminations are comprised of a layered structure, consisting of a base layer, a barrier layer and a solderable layer. The base layer is typically made of a composite of metal and glass or reactive oxide. It is baked on to the chip component at relatively high temperature (ca. 700C to 1000C). During baking, the metal mechanically and electrically connects with the electrode structure of the chip device and the glass or reactive oxide provides mechanical adhesion of the external electrical terminal to the chip. The metal used in this base layer is typically either silver or copper. Both are excellent conductors. However, copper oxidizes in air quickly and silver dissolves in molten solder quickly…enter the barrier layer.
The barrier layer is typically a layer of electrolytically deposited nickel. Nickel protects the base layer from solder dissolution as well as from oxidation, but Ni also oxidizes when exposed to the atmosphere. So we have to cover it with a suitable solderable layer that is oxidation resistant under normal storage conditions and does not “break the bank.” This is usually accomplished by an electrolytically deposited layer of tin.
With the above configuration, the industry has achieved an optimal solution for achieving excellent solderability, with good shelf life, at low cost. There is a problem however. The tin oxidizes over time, compromising solderability. Additionally, intermetallics of nickel and tin are formed. These Ni-Sn IMCs promote solder wetting at the interface between the Ni and Sn layers when the chip is new, but become a problem over time as they grow into the Sn coating and eventually reach the surface and oxidize and become unsolderable.
An illustration of a typical Ni-Sn IMC front growing into plated Sn after isothermal aging is shown below. From the figure, it is evident that the thickness of the IMC layer is highly variable.
Figure 1. Micrograph of a cross-section of a plated finish showing Ni-Sn IMCs1
Oxidized IMCs result in pin holes and dewets in the reflowed surface of the mounted component, rendering unacceptable soldered cosmetics (e.g., see first picture in this post).
The rate of IMC growth depends upon storage temperature and may be modeled using the relationship:
Z is thickness of the IMC layer at time t
Z0 is initial thickness of the IMC layer
A is a pre-exponential constant
n is a time exponent specific to the IMC chemistry
Q is activation energy of the IMC growth
R is universal gas constant
T is absolute temperature
“Doing the math,” Ni-Sn IMCs can grow to >20 µ-in thickness over 3 years when stored at 40C. Since the IMC layer varies significantly in thickness, the maximum IMC thickness would likely be considerably more. If the Sn plating has thin spots (not atypical) IMCs may be exposed and solderability compromised. Thus, it is important that your procurement specification have a requirement for a minimum Sn layer thickness of 80 µ-in or more.
In order to maximize shelf life of your surface mount chip components, store your inventory in a cool and dry place. Also, be sure to keep your stock as fresh as feasible, and to specify a minimum Sn thickness in your procurement specification. Combined, these practices will help you avoid IMC and Sn oxidation related solderability issues…TTFN! ; )
 P.L. Tu, et al., “GROWTH KINETICS OF INTERMETALLIC COMPOUNDS IN CHIP SCALE PACKAGE SOLDER JOINT,” Scripta mater. 44 (2001) 317–323.