Chip Components and Surface Mounting
Trillions of electronic chip components are installed within electronic assemblies every year using surface mount technology (SMT). Your smartphone, HDTV, car, etc., contain hundreds, if not thousands, of electronic devices assembled using SMT. The SMT process is simple, but highly refined, involving the precise location electronic components onto patterned solder paste deposits on a printed wiring board (PWB), using a pick and place (PnP) machine. The assembly is then heated, in order to flow the solder, and then cooled to achieve physical and electrical interconnects between each terminal of each component and the PWB circuit. Each mounted component must have suitable electrical, mechanical and cosmetic properties. This is all done billions of times per day with extremely low defect rates.
Minimizing Device-Related Defects
To enable these impressive statistics it is important that the chip components used to populate electronic assemblies are “up to the task.” Variation is the enemy, and chip components and their packaging need to be uniform in all dimensions as well as appearance. For example, if the device is domed the pick and place (PnP) machine may not be able to properly pick or place the chip. If the component termination is aberrant, the component may not align properly during reflow. If a component is too thick or too thin, it may experience stress during placement resulting in impact damage. If a device has a crack or chipout as delivered to SMT, it may be susceptible to humidity-related failure or to catastrophic cracking as the flaw develops over time.
If the chip packaging tape has dimensional variation, the component may not be properly oriented when addressed by the PnP head, resulting in improper placement or in damage of a component. If the devices are inconsistent in color, the vision system may miss a component.
Manufacturers are aware of these issues and have worked hard to achieve consistency. Thus, it is highly important to use a component supplier having an excellent track record of providing quality, consistent products to the electronics industry.
Minimizing SMT-Related Defects
Consistency is not just the job of the component supplier, however. SMT equipment must be carefully tuned and operated. PnP heads and nozzles must be new, clean and carefully adjusted, as failure to do so may result in impact damage or missed picks or alignment defects. Additionally, PWBs must be designed and fabricated precisely. Use of cleverly designed PWBs will help correct misalignment or other placement flaws during reflow. Solder paste deposition must also be precise. Too much solder can result in shorts while too little solder can result in opens. It is important to properly store and prepare solder pastes for use, and to make sure that the printer, stencil and squeegee are in good working condition and properly aligned. Temperature, atmosphere and belt rate must also be carefully managed during the reflow process, as “tombstoning” or other defects may occur. To avoid “tombstoning,” devices are oriented transversely during the re-flow process as well.
After reflow it is important to inspect each assembly using optical inspection (OI) and in circuit test (ICT). Certain flaws may be reworked at this stage. If multiple assemblies are contained within a panel, it is important to de-panel the assemblies carefully in order to avoid flex cracks or other damage to mounted components.
Illustrated below are four types of chip and SMT-related defects.
Chip and SMT-related defects
Finally, the assemblies are installed into a chassis. It is important that all components have proper clearance and that any tooling used for chassis assembly not mechanically interact with the electronic components in order to avoid tooling-related damage.
Precision and consistency are highly important in the pursuit of defect free electronic assemblies. Thus, it is very important to select the appropriate component supplier as well as to develop consistent SMT processes for defect free, high volume SMT assembly operations.